In the field of integrated circuits, devices, such as metal oxide semiconductor (MOS) transistors, may be used as switching devices. Typically, MOS transistors are formed having channel regions, source regions and drain regions in a semiconductor substrate. These MOS transistors may be referred to as bulk MOS transistors. Integrated circuit devices including, for example, complementary metal oxide semiconductor (CMOS) circuits that include N-channel bulk MOS transistors and P-channel bulk MOS transistors, may not provide adequate integration densities due to, for example, a latch-up phenomenon that occurs in CMOS circuits.
Recently, thin film transistors (TFTs) provided on the semiconductor substrate have been developed and used in order to improve the integration density of integrated circuit devices as well as the latch-up immunity of the CMOS circuits. For example, TFTs have been used in a unit cell of a static random access memory (SRAM). The SRAM may have improved power consumption and operating speeds relative to, for example, a dynamic random access memory (DRAM). Therefore, SRAMs are widely used as cache memory in, for example, computers and portable electronic devices.
A unit cell of an SRAM can generally be divided into two categories, a high-load resistor SRAM cell using a large resistor as a load device and a CMOS SRAM cell using a P-channel metal oxide semiconductor (PMOS) transistor as the load device. The CMOS SRAM cell may be, for example, a TFT SRAM cell or a bulk CMOS SRAM cell. The TFT SRAM cell may use the TFT as the load device. The bulk CMOS SRAM cell may use the bulk MOS transistor as the load device.
The bulk CMOS SRAM cell typically exhibits high cell stability relative to the TFT SRAM cell and the high-load resistor SRAM cell. Furthermore, the bulk CMOS SRAM cell exhibits excellent low voltage characteristics and low stand-by currents. This may be due to the use of a polycrystalline silicon (polysilicon) layer as a body layer in the fabrication of the TFT device, whereas transistors included in the bulk CMOS SRAM cell typically include a single crystalline silicon substrate. However, as discussed above, bulk CMOS SRAM cells typically exhibit low integration density and weak latch-up immunity relative to the TFT SRAM cell. Therefore, in order to provide a highly integrated SRAM having improved relative reliability, the characteristics of the load transistors used in the TFT SRAM cell may be improved.
Semiconductor devices having TFTs on a semiconductor substrate are discussed in U.S. Pat. No. 6,022,766 to Chen et al., entitled Semiconductor Structure Incorporating Thin Film Transistors and Methods for its Manufacture. As discussed in Chen, a conventional bulk MOS transistor may be formed on a single crystalline silicon substrate and a TFT may be provided on the bulk MOS transistor. One of the source region or the drain region of the bulk MOS transistor is electrically coupled to one of the source region or the drain region of the TFT through a metal plug. The metal plug may include, for example, tungsten. Accordingly, when the bulk MOS transistor and the TFT are, for example, an n-channel metal oxide semiconductor (NMOS) transistor and a positive channel metal oxide semiconductor (PMOS) transistor, respectively, the bulk MOS transistor may have an ohmic contact with the TFT film transistor through the metal plug.
Furthermore, a body layer of the TFT may be formed by, for example, depositing an amorphous silicon layer on a surface of the semiconductor substrate including the metal plug and crystallizing the amorphous silicon layer using, for example, an annealing process. The body layer may include a poly-silicon layer having large grains. In other words, it may be difficult to transform the body layer into a complete single crystalline silicon layer. Consequently, it may be difficult to form the TFT having electrical characteristics corresponding to the bulk MOS transistor.